Optimization of Die-Bonding Process Using Orthogonal Array Experiments
The chip of power transistor with die back metallization (Ti/Ni/Ag/Au) is bonded on the lead frame (Cu:>=99.96%) using the scrubbing method. The soft solder applied is Sn-Pb alloy. Voids appear in the bonding layer and reduce the reliability of the device. The average area of the voids measured by using the X-ray radiography amount to 9.3% of the examined surface, which lies beyond the accepted limit 7%. To reduce the voids in the bonding layer, a small number of experiments using orthogonal arrays are conducted systematically, which give the optimum combination of process parameters under a specified range of die-bonding machine. The amount of voids on the average now drops to 1.73%, far below the accepted limit. The method using orthogonal array experiments can be considered as a first step for the process redesign and prerequisite for a necessary numerical simulation.